FPGA Design Engineer
Company: ASML
Location: San Diego
Posted on: April 18, 2024
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Job Description:
IntroductionASML US, including its affiliates and subsidiaries,
bring together the most creative minds in science and technology to
develop lithography machines that are key to producing faster,
cheaper, more energy-efficient microchips. We design, develop,
integrate, market, and service these advanced machines, which
enable our customers - the world's leading chipmakers - to reduce
the size and increase the functionality of their microchips, which
in turn leads to smaller, more powerful consumer electronics. Our
headquarters are in Veldhoven, Netherlands, and we have 18 office
locations around the United States including main offices in
Chandler, Arizona, San Jose and San Diego, California, Wilton,
Connecticut, and Hillsboro, Oregon.Job MissionAs an FPGA
verification engineer, you will participate in a cross-functional
and collaborative team to ensure functionality of the target FPGA
design while developing a robust verification environment for
ASML's EUV Source and global FPGA community.This position requires
access to controlled technology, as defined in the Export
Administration Regulations (15 C.F.R. - 730, et seq.). Qualified
candidates must be legally authorized to access such controlled
technology prior to beginning work. Business demands may require
the Company to proceed with candidates who are immediately eligible
to access controlled technology.You must be work authorized in the
United States without the need for employer sponsorship.Job
DescriptionKey contributor for the FPGA verification plan and major
infrastructure development for a complex FPGA network.Collaborate
with FPGA architects, verification lead, design and test engineers
to verify RTL design, ensuring adequate coverage and maximizing
reusability.Develop verification plans, test benches and UVM
components to ensure code/functional coverage from block to
chip-to-chip level simulation.Perform requirement traceability via
Test Performance Specification (TPS) and capturing results in Test
Acceptance Report (TAR).Contribute to continuous improvement and
optimization of the UVM structure.Other duties as assigned.Job
description subject to change at any time.Education and
ExperienceBS or higher in EE, CS or related engineering
fields.Minimum of six (6) years' experience in FPGA targeted
verification.Highly proficient in System Verilog based UVM with
demonstrated experience creating UVM agents and components
(predictors, scoreboard, etc.) without templates.Familiar with VHDL
syntax and use for RTL design.Familiar with Xilinx SoC/Altera FPGA
target verification.Experience using Siemens UVM framework and
associated tooling environments (Questa Sim).Proficiency with
Python a plus.Familiar with revision control system and platforms
such as Git and Gitbucket.Skills & CompetenciesAbility to learn and
apply new information and/or skills.Demonstrated creative problem
solving for complex issues.Can read and interpret data,
information, and documents.Track record of completing assignments
with attention to detail and high degree of accuracy.Proven ability
to perform effectively in a demanding environment, within provided
timelines, and with changing workloads.Results driven; exhibits
ownership and accountability.Work independently or as part of a
team and follow through on assignments with minimal
supervision.Strong professional communication which is clear and
concise.Ability to establish and maintain cooperative working
relationships with co-workers.Diversity & InclusionASML is an Equal
Opportunity Employer that values and respects the importance of a
diverse and inclusive workforce. It is the policy of the company to
recruit, hire, train and promote persons in all job titles without
regard to race, color, religion, sex, age, national origin, veteran
status, disability, sexual orientation, or gender identity. We
recognize that diversity and inclusion is a driving force in the
success of our company.Other InformationThis position is located
on-site in San Diego, California. It requires onsite presence to
attend in-person work-related events, trainings and meetings and to
further ensure teamwork, collaboration and innovation.Routinely
required to sit; walk; talk; hear; use hands to keyboard, finger,
handle, and feel; stoop, kneel, crouch, twist, reach, and stretch.
Occasionally required to move around the campus.Occasionally lift
and/or move up to 20 pounds.Specific vision abilities required by
this job include close vision, color vision, peripheral vision,
depth perception, and ability to adjust focus.Must be willing to
work in a clean room environment, wearing coveralls, hoods,
booties, safety glasses and gloves for entire duration of
shift.While performing the duties of this job, the employee
routinely is required to sit; walk; talk; hear; use hands to
keyboard, finger, handle, and feel; stoop, kneel, crouch, twist,
reach, and stretch.EOE AA M/F/Veteran/DisabilityPotential
candidates will meet the education and experience requirements
provided on the above job description and excel in completing the
listed responsibilities for this role. All candidates receiving an
offer of employment must successfully complete a background check
band any other tests that may be required.Equal Opportunity
Employer Statement: ASML is an Equal Opportunity Employer that
values and respects the importance of a diverse and inclusive
workforce. It is the policy of the company to recruit, hire, train
and promote persons in all job titles without regard to race,
color, religion, sex, age, national origin, veteran status,
disability, sexual orientation, or gender identity. We recognize
that diversity and inclusion is a driving force in the success of
our company.Diversity and inclusionASML is an Equal Opportunity
Employer that values and respects the importance of a diverse and
inclusive workforce. It is the policy of the company to recruit,
hire, train and promote persons in all job titles without regard to
race, color, religion, sex, age, national origin, veteran status,
disability, sexual orientation, or gender identity. We recognize
that diversity and inclusion is a driving force in the success of
our company.Need to know more about applying for a job at ASML?
Read our frequently asked questions .
Keywords: ASML, Yorba Linda , FPGA Design Engineer, Engineering , San Diego, California
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